A Review on Reversible Quantum Comparator Circuits

Abstract

This article explores recent advances in reversible logic circuits, particularly focusing on efficient binary comparator designs. Notably, all the methods emphasize key features such as quantum cost, quantum delay, and garbage generation. Together the studies show significant improvements, from a 16.66% reduction in quantum cost to an impressive 63% reduction in quantum delay, achieved through techniques such as logic simplification, prefix clustering, and innovative gate designs. The study underscores the evolving landscape of reversible logic and its applications, including quantum computing and digital comparator optimization. This survey paper reviews various approaches to designing efficient reversible binary comparators. These approaches involve the use of gates such as Peres gates, Feynman gates, reversible NOT gates, controlled V gates, and controlled V+ gates.