Design of 16-bit Pipelined RISC Processor

Abstract

This paper presents the design of efficient and high throughput 16 bit pipelined RISC Processor. The design is carried out considering the pipeline problem, speed with external memory, coding density and clock frequency for cost effectiveness and higher performance processor design. Paper describes about the architecture, programming model, synthesis results and analysis of the design. The coding is carried out in Verilog HDL and functionality is verified through simulation and test benches at different stages including behavioral and gate level RTL code using Modelsim (Mentor Graphics). The synthesis part is done using Leonardo Spectrum of Mentor Graphics. The presented design has throughput ~167 MIPS at 500 MHz, which shows better performance at a particular frequency.